1. Field of the Invention
The field of the invention pertains to random access computer memories RAM's of the magnetic core or MOS type and particularly to a circuit and method for connecting data lines to a data bus.
2. Description of the Prior Art
Random access memories either of the magnetic core or of the MOS type generally require additional operations to be performed on the memory after read-out or write operations. For example, in the magnetic core memory read-out is effected by destroying the data content of the memory. To preserve the data content of the memory, a further write operation is required after read-out. Accordingly, in one type of prior art memory array data read out is latched to a data bus which preserves and presents this data to a data-latch during one memory cycle. In this type of a memory array known as a latched memory array data read out of the memory will remain on the data bus for one entire memory cycle even though the memory enable signal is removed, unless the data bus is disabled in some other manner. Once the data bus has presented the data to the data latch during one cycle, it may be desirable to utilize the remainder of that cycle by initiating a read operation in a second memory array and present the data-out to the data bus. However, since the data bus with this type of latched memory array remains latched to the previous data, it cannot be utilized during that memory cycle unless the data bus is disabled i.e. disconnected from the first memory array by presenting a high impedance to it. In prior art devices a tri-state buffer circuit is utilized to disconnect the latched memory arrays to the data bus. A typical tri-state buffer circuit being utilized is the SN75367 commercially available from Texas Instruments Inc. In normal operation the tri-state buffer circuit presents a high impedance to the memory array when its control is true i.e. its internally generated clock signal. When the control of the tri-state buffer circuit is not true, it presents a high or low state. (A tri-state circuit has 3 output characteristics -- high state, low state and high impedance state).
However, there are some serious disadvantages in utilizing this prior art tri-state buffer circuit. The main disadvantage is that it dissipates a considerable amount of power in operation since control of the different states of the circuit is not accomplished by manipulating the power input; hence power is constantly applied to the tri-state buffer circuit. In this day of energy conservation, this is intolerable and requires corrections.
What is required therefore is a new circuit or a new concept of operation which dissipates a small amount of power and is low in operating cost and yet simulates the states of prior art tri-state buffer circuits.